SH7729R Datasheet, PDF (535/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

SCPDR Bit 0—Serial Port Break Data (SCP0DT): Specifies the serial port RxD pin input data
and TxD pin output data. The TxD pin output condition is specified by the SCP0MD0 and
SCP0MD1 bits. When the TxD pin is set to output mode, the value of the SCP0DT bit is output to
the TxD pin. The RxD pin value is read from the SCP0DT bit regardless of the values of the
SCP0MD0 and SCP0MD1 bits, if RE in SCSCR is set to 1. The initial value of this bit after a
power-on reset is undefined.
Bit 0:
SCP0DT
0
1
Description
I/O data is low
I/O data is high
(Initial value)
Block diagrams of the SCI I/O port pins are shown in figures 15.2, 15.3, and 15.4.
15.2.9 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset, and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
Asynchronous mode: N =
Pφ
× 10⁶ – 1
64 × 2^{2n – 1} × B
Synchronous mode: N =
Pφ
× 10⁶ – 1
8 × 2^{2n – 1} × B
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 15.3.)
Rev. 5.0, 09/03, page 489 of 806