SH7729R Datasheet, PDF (42/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 4.4 Types of Reset ........................................................................................................ 133
Table 5.1 Cache Specifications............................................................................................... 143
Table 5.2 LRU and Way Replacement ................................................................................... 145
Table 5.3 Register Configuration............................................................................................ 145
Table 5.4 LRU and Way Replacement (when W2LOCK=1) ................................................. 147
Table 5.5 LRU and Way Replacement (when W3LOCK=1) ................................................. 147
Table 5.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)..................... 148
Table 6.1 X/Y Memory Specifications ................................................................................... 157
Table 7.1 INTC Pins ............................................................................................................... 163
Table 7.2 INTC Registers ....................................................................................................... 164
Table 7.3 IRL3–IRL0/IRLS3–IRLS0 Pins and Interrupt Levels ............................................ 167
Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) ........................... 170
Table 7.5 Interrupt Exception Handling Sources and Priority (IRL Mode)............................ 172
Table 7.6 Interrupt Levels and INTEVT Codes...................................................................... 174
Table 7.7 Interrupt Request Sources and IPRA–IPRE............................................................ 175
Table 7.8 Interrupt Response Time......................................................................................... 190
Table 8.1 UBC Registers ........................................................................................................ 196
Table 8.2 Data Access Cycle Addresses and Operand Size Comparison Conditions............. 216
Table 8.3 BSA Values Stored in Exception Handling before Execution of Branch
Destination Instruction............................................................................................ 219
Table 9.1 Power-Down Modes ............................................................................................... 228
Table 9.2 Pin Configuration.................................................................................................... 229
Table 9.3 Register Configuration............................................................................................ 229
Table 9.4 Register States in Standby Mode ............................................................................ 234
Table 10.1 CPG Pins and Functions ......................................................................................... 252
Table 10.2 CPG Register .......................................................................................................... 252
Table 10.3 Clock Operating Modes .......................................................................................... 253
Table 10.4 Available Combinations of Clock Mode and FRQCR Values................................ 254
Table 10.5 Register Configuration............................................................................................ 261
Table 11.1 BSC Pins................................................................................................................. 272
Table 11.2 BSC Registers......................................................................................................... 274
Table 11.3 Physical Address Space Map.................................................................................. 276
Table 11.4 Correspondence between External Pins (MD4 and MD3) and Memory Size......... 277
Table 11.5 PCMCIA Interface Characteristics ......................................................................... 278
Table 11.6 PCMCIA Support Interface .................................................................................... 279
Table 11.7 32-Bit External Device/Big-Endian Access and Data Alignment .......................... 306
Table 11.8 16-Bit External Device/Big-Endian Access and Data Alignment .......................... 307
Table 11.9 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 308
Table 11.10 32-Bit External Device/Little-Endian Access and Data Alignment........................ 309
Table 11.11 16-Bit External Device/Little-Endian Access and Data Alignment........................ 309
Table 11.12 8-Bit External Device/Little-Endian Access and Data Alignment.......................... 310
Table 11.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output ....... 324
Rev. 5.0, 09/03, page xlii of xlvi