SH7729R Datasheet, PDF (527/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

15.2.6 Serial Control Register (SCSCR)
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive
clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a
reset and in standby or module standby mode.
Bit:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SCSSR) is set to 1 due to transfer of serial transmit data from SCTDR to SCTSR.
Bit 7: TIE
0
1
Description
Transmit-data-empty interrupt request (TXI) is disabled
(Initial value)
The TXI interrupt request can be cleared by reading TDRE after it has been set
to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TXI) is enabled
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set
to 1 due to transfer of serial receive data from SCRSR to SCRDR. It also enables or disables
receive-error interrupt (ERI) requests.
Bit 6: RIE
0
1
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
disabled
(Initial value)
RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error
flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or
by clearing RIE to 0.
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled
Rev. 5.0, 09/03, page 481 of 806