SH7729R Datasheet, PDF(183/855 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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SH7729R Datasheet, PDF (183/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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ï£§ Operations: PC and SR of the instruction that generated the exception are saved to SPC and

SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1

and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than

H'Fxxx is decoded, operation cannot be guaranteed.

â¢ Illegal slot instruction

ï£§ Conditions:

a. When undefined code in a delay slot is decoded

Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,

BF/S

b. When an instruction that rewrites PC in a delay slot is decoded

Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,

BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR

c. When a privileged instruction in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access

GBR with LDC/STC are not privileged instructions and therefore do not apply.

d. When a DSP instruction in a delay slot is decoded without DSP extension (SR.DSP=0)

DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,

DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn,

STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm,

RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,

STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn,

LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx

ï£§ Operations: PC of the previous delay branch instruction is saved to SPC. SR of the

instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,

MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an

undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.

â¢ User break point trap

ï£§ Conditions: When a break condition set in the user break controller is satisfied

ï£§ Operations: When a post-execution break occurs, PC of the next instruction after the

instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of the

instruction that set the break point is set in SPC. SR when the break occurs is set in SSR.

H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs

to PC = VBR + H'0100. See section 8, User Break Controller, for more information.

â¢ DMA address error

ï£§ Conditions:

a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)

b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,

4n + 3)

Rev. 5.0, 09/03, page 137 of 806

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