SH7729R Datasheet, PDF (23/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.3.8 Examples of Use................................................................................................... 220
8.3.9 Notes .................................................................................................................... 225
Section 9 Power-Down Modes......................................................................................... 227
9.1 Overview ........................................................................................................................... 227
9.1.1 Power-Down Modes............................................................................................. 227
9.1.2 Pin Configuration ................................................................................................. 229
9.1.3 Register Configuration ......................................................................................... 229
9.2 Register Descriptions......................................................................................................... 229
9.2.1 Standby Control Register (STBCR) ..................................................................... 229
9.2.2 Standby Control Register 2 (STBCR2) ................................................................ 231
9.3 Sleep Mode........................................................................................................................ 233
9.3.1 Transition to Sleep Mode ..................................................................................... 233
9.3.2 Canceling Sleep Mode.......................................................................................... 233
9.4 Standby Mode.................................................................................................................... 234
9.4.1 Transition to Standby Mode ................................................................................. 234
9.4.2 Canceling Standby Mode ..................................................................................... 235
9.4.3 Clock Pause Function........................................................................................... 236
9.5 Module Standby Function ................................................................................................. 237
9.5.1 Transition to Module Standby Function............................................................... 237
9.5.2 Clearing Module Standby Function...................................................................... 237
9.6 Timing of STATUS Pin Changes ...................................................................................... 238
9.6.1 Timing for Resets ................................................................................................. 238
9.6.2 Timing for Canceling Standby ............................................................................. 240
9.6.3 Timing for Canceling Sleep Mode ....................................................................... 243
9.7 Hardware Standby Mode................................................................................................... 245
9.7.1 Transition to Hardware Standby Mode ................................................................ 245
9.7.2 Canceling Hardware Standby Mode..................................................................... 245
9.7.3 Hardware Standby Mode Timing ......................................................................... 246
Section 10 On-Chip Oscillation Circuits....................................................................... 249
10.1 Overview ........................................................................................................................... 249
10.1.1 Features ................................................................................................................ 249
10.2 Overview of CPG .............................................................................................................. 250
10.2.1 CPG Block Diagram............................................................................................. 250
10.2.2 CPG Pin Configuration ........................................................................................ 252
10.2.3 CPG Register Configuration................................................................................. 252
10.3 Clock Operating Modes..................................................................................................... 253
10.4 Register Descriptions......................................................................................................... 257
10.4.1 Frequency Control Register (FRQCR) ................................................................. 257
10.5 Changing the Frequency.................................................................................................... 259
10.5.1 Changing the Multiplication Rate ........................................................................ 259
10.5.2 Changing the Division Ratio ................................................................................ 259
Rev. 5.0, 09/03, page xxiii of xlvi