SH7729R Datasheet, PDF (256/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bit 6: PCBB
0
1
Description
PC break of channel B is set before instruction execution
PC break of channel B is set after instruction execution
(Initial value)
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bit 3: SEQ
0
1
Description
Channels A and B are compared as independent conditions
Channels A and B are compared as a sequential condition
(Initial value)
Bits 2 and 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—Execution Times Break Enable (ETBE): Enables the execution-times break condition on
channel B only. If this bit is 1 (break enabled), a user break is issued when the number of break
conditions matches the number of execution times specified by the BETR register.
Bit 0: ETBE
0
1
Description
Execution-times break condition is masked on channel B
Execution-times break condition is enabled on channel B
(Initial value)
8.2.10 Break Execution Times Register (BETR)
Bit: 15
14
13
12
—
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
11
10
9
8
0
0
0
0
R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.0, 09/03, page 210 of 806