SH7729R Datasheet, PDF (284/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

9.6 Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 9.1 to 9.8.
9.6.1 Timing for Resets
Power-On Reset
CKIO, CKIO2^*4
RESETP
PLL settling
time
STATUS
Normal^*2
Reset^*1
Normal^*2
RESETOUT
0 to 5 Bcyc^*3
0 to 30 Bcyc^*3
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Normal: LL (STATUS1 low, STATUS0 low)
3. Bcyc: Bus clock cycle
4. CKIO2 output can only be used in clock modes 0, 1, and 2.
Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output
Rev. 5.0, 09/03, page 238 of 806