SH7729R Datasheet, PDF (17/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
Page
24.3.6 Synchronous 733
DRAM Timing
Figure 24.31
Synchronous DRAM
Burst Read Bus Cycle
(RAS Down, Same Row
Address, CAS Latency
= 2)
Description
Tnop cycle deleted from figure
Tc1
Tc2 Tc3/Td1 Tc4/Td2 Td3
Td4
CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
tAD
tAD
tAD
tCSD3
tRWD
tRASD2
tCASD2
tDQMD
D31 to D0
BS
Row address
tAD
Read command
tAD
Column address
tAD
tCSD3
tRWD
tCASD2
tRDS2 tRDH2
tDQMD
tRDS2 tRDH2
tBSD
tBSD
CKE
DACKn
(High)
tDAKD1
tDAKD1
24.3.8 Peripheral
751
Module Signal Timing
Figure 24.52 I/O Port
Timing
A.2 Pin Specifications 767
Table A.2 Pin
Specifications
(Before) PORT 7 to 0 (read) (B:P clock ratio =1:2) →
(After) PORT 7 to 0 (read) (B:P clock ratio =2:1)
(Before) PORT 7 to 0 (read) (B:P clock ratio =1:4) →
(After) PORT 7 to 0 (read) (B:P clock ratio =4:1)
Function information amended for VCC–RTC, VCC–PLL1, VCC–
PLL2, and VCC
Pin Pin No. Pin No. I/O
(FP-208C, (BP-
FP-208E) 240A)
Function
VCC– 3
RTC
E2
Power RTC oscillator power
supply supply
(2.0/1.9/1.8/1.7 V)
VCC– 145
PLL1 150
VCC–
PLL2
F16,
E17
Power PLL power supply
supply (2.0/1.9/1.8/1.7 V)
VCC 29, 81,
L3, L4,
Power Internal power supply
134, 154, U11, T11, supply (2.0/1.9/1.8/1.7 V)
175
J17, J16,
E18, C19,
C12, D12
Rev. 5.0, 09/03, page xvii of xlvi