SH7729R Datasheet, PDF (247/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.4 Break Address Register B (BARB)
Bit:
Initial value:
R/W:
31
BAB31
0
R/W
30
BAB30
0
R/W
29
BAB29
0
R/W
28
BAB28
0
R/W
27
BAB27
0
R/W
26
BAB26
0
R/W
25
BAB25
0
R/W
24
BAB24
0
R/W
Bit:
Initial value:
R/W:
23
BAB23
0
R/W
22
BAB22
0
R/W
21
BAB21
0
R/W
20
BAB20
0
R/W
19
BAB19
0
R/W
18
BAB18
0
R/W
17
BAB17
0
R/W
16
BAB16
0
R/W
Bit:
Initial value:
R/W:
15
BAB15
0
R/W
14
BAB14
0
R/W
13
BAB13
0
R/W
12
BAB12
0
R/W
11
BAB11
0
R/W
10
BAB10
0
R/W
9
BAB9
0
R/W
8
BAB8
0
R/W
Bit:
Initial value:
R/W:
7
BAB7
0
R/W
6
BAB6
0
R/W
5
BAB5
0
R/W
4
BAB4
0
R/W
3
BAB3
0
R/W
2
BAB2
0
R/W
1
BAB1
0
R/W
0
BAB0
0
R/W
BARB is a 32-bit readable/writable register that specifies the address used as a break condition in
channel B. Control bits XYE and XYS in BBRB select an address bus for break condition B. If
XYE is 0, then BARB specifies the break address on the logic or internal bus, LAB or IAB. If
XYE is 1, then BAB31–16 specifies the break address on XAB (bits 15–1) and BAB15–0
specifies the break address on YAB (bits 15–1). However, one of two address buses must be
chosen for the break. BARB is initialized to H'00000000 by a power-on reset.
XYE = 0
XYE = 1
BAB31–16
L(I) AB31–16
XAB15–1 (XYS = 0)
BAB15–0
L(I) AB15–0
YAB15–1 (XYS = 1)
Rev. 5.0, 09/03, page 201 of 806