SH7729R Datasheet, PDF (680/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.3.2 Port B Data Register (PBDR)
Bit:
Initial value:
R/W:
7
PB7DT
0
R/W
6
PB6DT
0
R/W
5
PB5DT
0
R/W
4
PB4DT
0
R/W
3
PB3DT
0
R/W
2
PB2DT
0
R/W
1
PB1DT
0
R/W
0
PB0DT
0
R/W
The port B data register (PBDR) is an 8-bit readable/writable register that stores data for pins
PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0. When the pin function
is general output port, if the port is read the value of the corresponding PBDR bit is returned
directly. When the function is general input port, if the port is read the corresponding pin level is
read. Table 20.4 shows the function of PBDR.
PBDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Table 20.4 Port B Data Register (PBDR) Read/Write Operations
PBnMD1
0
1
PBnMD0
0
1
0
1
Pin State
Other function
(See table 19.1)
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Read
PBDR value
PBDR value
Pin state
Pin state
Write
Value is written to PBDR, but does not
affect pin state
Write value is output from pin
Value is written to PBDR, but does not
affect pin state
Value is written to PBDR, but does not
affect pin state
(n = 7 to 0)
Rev. 5.0, 09/03, page 634 of 806