SH7729R Datasheet, PDF (696/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.11.2 Port K Data Register (PKDR)
Bit:
Initial value:
R/W:
7
PK7DT
0
R/W
6
PK6DT
0
R/W
5
PK5DT
0
R/W
4
PK4DT
0
R/W
3
PK3DT
0
R/W
2
PK2DT
0
R/W
1
PK1DT
0
R/W
0
PK0DT
0
R/W
The port K data register (PKDR) is an 8-bit readable/writable register that stores data for pins
PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function
is general output port, if the port is read, the value of the corresponding PKDR bit is returned
directly. When the function is general input port, if the port is read, the corresponding pin level is
read. Table 20.20 shows the function of PKDR.
PKDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Table 20.20 Port K Data Register (PKDR) Read/Write Operations
PKnMD1
0
1
PKnMD0
0
1
0
1
Pin State
Other function
(See table 19.1)
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Read
PKDR value
PKDR value
Pin state
Pin state
Write
Value is written to PKDR, but does not
affect pin state
Write value is output from pin
Value is written to PKDR, but does not
affect pin state
Value is written to PKDR, but does not
affect pin state
(n = 0 to 7)
Rev. 5.0, 09/03, page 650 of 806