SH7729R Datasheet, PDF (445/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

SAR3
D _DAR3
M
A Temporary
C buffer
Data
buffer
Memory
Transfer source
module
Transfer destination
module
When the value in SAR3 is an address, the memory data is read and
the value is stored in the temporary buffer. The value to be read must
be 32 bits since it is used for the address.
First and second bus cycles
SAR3
D _DAR3
M
A Temporary
C buffer
Data
buffer
Memory
Transfer source
module
Transfer destination
module
When the value in the temporary buffer is an address, the data is read
from the transfer source module to the data buffer.
Third bus cycle
SAR3
D _DAR3
M
A Temporary
C buffer
Data
buffer
Memory
Transfer source
module
Transfer destination
module
When the value in DAR3 is an address, the value in the data buffer is
written to the transfer source module.
Fourth bus cycle
Note: This example shows memory, the transfer source module, and
the transfer destination module; in practice, any module can be
connected in the addressing space.
Figure 12.9 Indirect Address Operation in Dual Address Mode
(When External Memory Space has a 16-Bit Width)
Rev. 5.0, 09/03, page 399 of 806