SH7729R Datasheet, PDF (718/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

21.4.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 21.6 shows the A/D
conversion timing. Table 21.4 indicates the A/D conversion time.
As indicated in figure 21.6, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 21.4.
In multi mode and scan mode, the conversion time values given in table 21.4 apply to the first
conversion. In the second and subsequent conversions, the conversion time is fixed at 256 states
when CKS = 0 in ADCSR, or 128 states when CKS = 1. In both cases, the CKS bit should be set
according to the Pφ frequency so that the conversion time is within the range shown in table 24.10
in section 24, Electrical Characteristics.
*1
Pφ
Address *2
Write
signal
Input sampling
timing
ADF
t_D
t_SPL
t_CONV
t_D
t_SPL
t_CONV
Notes:
A/D conversion start delay
Input sampling time
A/D conversion time
1. ADCSR write cycle
2. ADCSR address
Figure 21.6 A/D Conversion Timing
Rev. 5.0, 09/03, page 672 of 806