SH7729R Datasheet, PDF (251/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.8 Break Bus Cycle Register B (BBRB)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
XYE XYS
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit:
Initial value:
R/W:
7
CDB1
0
R/W
6
CDB0
0
R/W
5
IDB1
0
R/W
4
IDB0
0
R/W
3
RWB1
0
R/W
2
RWB0
0
R/W
1
SZB1
0
R/W
0
SZB0
0
R/W
Break bus cycle register B (BBRB) is a 16-bit readable/writable register that specifies (1) logic or
internal bus (L or I bus), X bus, or Y bus, (2) CPU cycle or DMAC cycle, (3) instruction fetch or
data access, (4) read/write, and (5) operand size in the break conditions of channel B. BBRB is
initialized to H'0000 by a power-on reset.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable (XYE): Selects the logic or internal bus (L or I bus) or X/Y
memory bus as the bus of the channel B break condition.
Bit 9: XYE
0
1
Description
Internal bus (I bus) selected for the channel B break condition
X/Y memory bus (X/Y bus) selected for the channel B break condition
Bit 8—X or Y Memory Bus Select (XYS): Selects the X bus or the Y bus as the bus of the
channel B break condition.
Bit 8: XYS
0
1
Description
X bus selected for the channel B break condition
Y bus selected for the channel B break condition
Rev. 5.0, 09/03, page 205 of 806