SH7729R Datasheet, PDF (431/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

12.2.5 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the
DMAC transfer mode. Writing to bits 15 to 10 and bits 7 to 3 is invalid in this register; 0 is always
read if these bits are read.
DMAOR is initialized to 0 by a power-on reset, and in hardware standby mode or software
standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
PR1 PR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
—
—
—
—
—
AE
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R/(W)^*
Note: * Only 0 can be written to the AE and NMIF bits after 1 is read.
1
NMIF
0
R/(W)^*
0
DME
0
R/W
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 9 and 8—Priority Mode Bits 1 and 0 (PR1, PR0): Select the priority level between
channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1
0
0
1
1
Bit 8: PR0
0
1
0
1
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round-robin
(Initial value)
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.0, 09/03, page 385 of 806