SH7729R Datasheet, PDF (484/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Channels 0 and 1 TCR Bit Configuration:
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Channel 2 TCR Bit Configuration:
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
ICPF UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit:
Initial value:
R/W:
7
ICPE1
0
R/W
6
ICPE0
0
R/W
5
UNIE
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Bits 15 to 10, 9 (except TCR2), 7, and 6 (except TCR2)—Reserved: These bits are always read
as 0. The write value should always be 0.
Bit 9—Input Capture Interrupt Flag (ICPF): A function of channel 2 only: the flag is set when
input capture is requested via the TCLK pin.
Bit 9: ICPF
Description
0
No input capture request has been issued
Clearing condition: When 0 is written to ICPF
(Initial value)
1
Input capture has been requested via the TCLK pin
Setting condition: When input capture is requested via the TCLK pin^*
Note: * Contents do not change when 1 is written to ICPF.
Rev. 5.0, 09/03, page 438 of 806