SH7729R Datasheet, PDF (562/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 15.16 shows an example of SCI receive operation using a multiprocessor format.
Start Data
1 _bit (ID1)
Serial
data
0 D₀ D₁
MPIE
Stop Start Data
MPB bit bit (data 1)
D₇ 1 1 0 D₀ D₁
Stop
MPB bit
1
D₇
0
1 ^{Idle (mark)}
state
RDRF
RDR
value
ID1
RXI interrupt request
RXI interrupt handler
(multiprocessor interrupt) reads RDR data and
generated, MPIE = 0
clears RDRF bit to 0
Example: Own ID does not match data
ID is not station's
ID, so MPIE bit is
set to 1 again
No RXI interrupt
generated;
RDR state
is maintained
Figure 15.16 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Rev. 5.0, 09/03, page 516 of 806