SH7729R Datasheet, PDF (111/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Arithmetic Operation Instructions
Table 2.21 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
CMP/PL Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
If Rn = Rm, 1 → T
0011nnnnmmmm0000
If Rn ≥ Rm with
unsigned data, 1 → T
If Rn ≥ Rm with signed
data, 1 → T
If Rn > Rm with
unsigned data, 1 → T
If Rn > Rm with signed
data, 1 → T
If Rn ≥ 0, 1 → T
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010001
If Rn > 0, 1 → T
0100nnnn00010101
If Rn and Rm have an
equivalent byte, 1 → T
0010nnnnmmmm1100
Single-step division
(Rn/Rm)
0011nnnnmmmm0100
MSB of Rn → Q, MSB 0010nnnnmmmm0111
of Rm → M, M ^ Q → T
0 → M/Q/T
0000000000011001
Signed operation of
0011nnnnmmmm1101
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Unsigned operation of 0011nnnnmmmm0101
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Privileged
Mode
Cycles T Bit
—
1
—
—
1
—
—
1
Carry
—
1
Overflow
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Comparison
result
—
1
Calculation
result
—
1
Calculation
result
—
1
0
—
2(5)^*1 —
—
2(5)^*1 —
Rev. 5.0, 09/03, page 65 of 806