SH7729R Datasheet, PDF (526/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous
mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because
no stop bits are added.
When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
0
1
Description
One stop bit
(Initial value)
When transmitting, a single 1-bit is added at the end of each transmitted
character.
Two stop bits
When transmitting, two 1-bits are added at the end of each transmitted character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit
setting is used only in asynchronous mode; it is ignored in synchronous mode. For the
multiprocessor communication function, see section 15.3.3, Multiprocessor Communication.
Bit 2: MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on-
chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16, and Pφ/64. For further
information on the clock source, bit rate register settings, and baud rate, see section 15.2.9, Bit
Rate Register (SCBRR).
Bit 1: CKS1
Bit 0: CKS0
0
0
1
1
0
1
Note: Pφ: Peripheral clock
Description
Pφ
Pφ/4
Pφ/16
Pφ/64
(Initial value)
Rev. 5.0, 09/03, page 480 of 806