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SH7729R Datasheet, PDF (110/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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Instruction
Operation
MOV.W Rm,@(R0,Rn)
Rm â (R0 + Rn)
MOV.L Rm,@(R0,Rn)
Rm â (R0 + Rn)
MOV.B @(R0,Rm),Rn
(R0 + Rm) â Sign
extension â Rn
MOV.W @(R0,Rm),Rn
(R0 + Rm) â Sign
extension â Rn
MOV.L @(R0,Rm),Rn
(R0 + Rm) â Rn
MOV.B R0,@(disp,GBR) R0 â (disp + GBR)
MOV.W R0,@(disp,GBR) R0 â (disp à 2 + GBR)
MOV.L R0,@(disp,GBR) R0 â (disp à 4 + GBR)
MOV.B @(disp,GBR),R0 (disp + GBR) â Sign
extension â R0
MOV.W @(disp,GBR),R0 (disp à 2 + GBR) â
Sign extension â R0
MOV.L @(disp,GBR),R0 (disp à 4 + GBR) â R0
MOVA @(disp,PC),R0 disp à 4 + PC â R0
MOVT Rn
T â Rn
SWAP.B Rm,Rn
Rm â Swap lowest two
bytes â REG
SWAP.W Rm,Rn
Rm â Swap two
consecutive words â Rn
XTRCT Rm,Rn
Rm: Middle 32 bits of
Rn â Rn
Code
0000nnnnmmmm0101
0000nnnnmmmm0110
0000nnnnmmmm1100
0000nnnnmmmm1101
0000nnnnmmmm1110
11000000dddddddd
11000001dddddddd
11000010dddddddd
11000100dddddddd
11000101dddddddd
11000110dddddddd
11000111dddddddd
0000nnnn00101001
0110nnnnmmmm1000
0110nnnnmmmm1001
0010nnnnmmmm1101
Privileged
Mode
Cycles T Bit
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
â
1
â
Rev. 5.0, 09/03, page 64 of 806
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