SH7729R Datasheet, PDF (50/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
Features
User break
• Two break channels
controller (UBC) _{• Addresses, data values, type of access, and data size can all be set as break}
conditions
• Supports a sequential break function
Bus state
• Physical address space divided into six areas (area 0, areas 2 to 6), each a
controller (BSC)
maximum of 64 Mbytes, with the following features settable for each area:
 Bus size (8, 16, or 32 bits)
 Number of wait cycles (also supports a hardware wait function)
 Specifying the memory to be connected to each area enables direct
connection to SRAM, DRAM, synchronous DRAM, and burst ROM
 Supports PCMCIA interface (2 channels)
 Outputs chip select signal (CS0, CS2–CS6) for corresponding area
• Synchronous DRAM refresh function
 Programmable refresh interval
 Supports self-refresh mode
• Synchronous DRAM burst access function
• Big or little endian can be set
User debugging
Interface (UDI)
• E10A emulator support
• JTAG-compliant
• Realtime branch trace
• 1-kbyte on-chip RAM for fast emulation program execution
Timer (TMU)
• 3-channel auto-reload-type 32-bit timer
• Input capture function
• Selection of six counter input clocks
• Maximum resolution: 2 MHz
Realtime clock
(RTC)
• Built-in clock, calendar functions, and alarm functions
• On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Serial communi- •
cation interface 0
(SCI0)
•
•
Asynchronous mode or clock synchronous mode can be selected
Full-duplex communication
Supports smart card interface
Serial communi- •
cation interface 1
(SCI1)
•
•
16-byte FIFO for transmission/reception
DMA transfer capability
IrDA: interface based on 1.0
Rev. 5.0, 09/03, page 4 of 806