SH7729R Datasheet, PDF (369/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

SH7729R
A14
A13
A12
····
····
A1
CKIO
CKE
CSn
RAS3x
CASx
RD/WR
D15
····
····
D0
DQMLU
DQMLL
64M synchronous DRAM
(1M × 16 bit × 4 bank)
A13
A12
A11
····
····
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
····
····
DQ0
DQMU
DQML
Figure 11.13 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMX2-AMX0 in MCR. Table
11.13 shows the relationship between the address multiplex specification bits and the bits output at
the address pins.
A25–A16 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to the SH7729R, it performs
longword address specification. Connection should therefore be made in the following order: with
a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of the SH7729R, then
connect pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to
pin A1 of the SH7729R, then connect pin A1 to pin A2.
Rev. 5.0, 09/03, page 323 of 806