SH7729R Datasheet, PDF (698/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.12.2 Port L Data Register (PLDR)
Bit:
Initial value:
R/W:
7
PL7DT
0
R
6
PL6DT
0
R
5
PL5DT
0
R
4
PL4DT
0
R
3
PL3DT
0
R
2
PL2DT
0
R
1
PL1DT
0
R
0
PL0DT
0
R
The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to
PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general
input port, if the port is read, the corresponding pin level is read. Table 20.22 shows the function
of PLDR.
PLDR is initialized to H'00 by power-on reset. It retains its previous value in software standby
mode and sleep mode, and in a manual reset.
As port L also has analog pin functions, it has no pull-up MOS.
Table 20.22 Port L Data Register (PLDR) Read/Write Operation
PLnMD1 PLnMD0 Pin State
Read
0
0
Other function H'00
(See table 19.1)
1
Reserved
H'00
1
0
Input
Pin state
1
Input
Pin state
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
(n = 0 to 7)
Rev. 5.0, 09/03, page 652 of 806