SH7729R Datasheet, PDF (133/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 2.33 DC Bit Update Definitions
CS [2:0] Condition Mode Description
0 0 0 Carry or borrow
mode
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
When a shift instruction (PSHA or PSHL) is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
0 0 1 Negative value
mode
When an ALU arithmetic operation or arithmetic shift (PSHA)
operation is executed, the MSB of the result, including the guard
bits, is copied into the DC bit.
When an ALU logical operation or logical shift (PSHL) operation is
executed, the MSB of the result, excluding the guard bits, is copied
into the DC bit.
0 1 0 Zero value mode The DC bit is set if the result of an ALU arithmetic or shift operation
is all-zeros, and is cleared otherwise.
0 1 1 Overflow mode
The DC bit is set if the result of an ALU arithmetic operation or
arithmetic shift (PSHA) operation exceeds the destination register
range, excluding the guard bits, and is cleared otherwise.
When an ALU logical operation or logical shift (PSHL) operation is
executed, the DC bit is always cleared.
1 0 0 Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is
mode
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
In case of arithmetic operation
DC = 0; In case of logical operation
1 0 1 Signed greater-or-
equal mode
If the result of an ALU arithmetic operation or arithmetic shift
(PSHA) operation exceeds the destination register range, including
the guard bits (ìoverrangeî), the definition is the same as in
negative value mode. If the result is not over-range, the definition is
the negative value mode with the DC bit inverted.
When an ALU logical operation or logical shift (PSHL) operation is
executed, the DC bit is always cleared.
DC = ~(negative value ^ over-range);
In case of arithmetic operation
DC = 0 ; In case of logical operation
1 1 0 Reserved
1 1 1 Reserved
Rev. 5.0, 09/03, page 87 of 806