SH7729R Datasheet, PDF (267/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3. Register specifications
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
• Channel A
Address: H'00027128, Address mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/write/word
No ASID check is included
• Channel B
Address: H'00031415, Address mask: H'00000000
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
No ASID check is included
On channel A, no user break occurs since an instruction fetch is not a write cycle. On channel
B, no user break occurs since an instruction fetch is performed for an even address.
4. Register specifications
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
• Channel A
Address: H'00037226, Address mask: H'00000000, ASID: H'80
Bus cycle: CPU/instruction fetch (before instruction execution)/write/word
• Channel B
Address: H'0003722E, Address mask: H'00000000, ASID: H'70
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read/word
Since the instruction fetch is not a write cycle on channel A, a sequential condition is not
matched. Therefore, no user break occurs.
Rev. 5.0, 09/03, page 221 of 806