SH7729R Datasheet, PDF (465/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Conditions for Ending on All Channels Simultaneously: Transfers on all channels end (1) when
the NMIF (NMI flag) bit is set to 1 in DMAOR, or (2) when the DME bit in DMAOR is cleared to
0.
• Transfer ending when the NMIF bit is set to 1 in DMAOR: When an NMI interrupt occurs, the
NMIF bit is set to 1 in DMAOR and all channels stop their transfers according to the
conditions in (a) to (d) described above, and pass the bus to an other bus master. Consequently,
even if the NMI bit is set to 1 during transfer, SAR, DAR, DMATCR are updated. The TE bit
is not set. To resume transfer after NMI interrupt exception handling, clear the NMIF bit to 0.
At this time, if there are channels that should not be restarted, clear the corresponding DE bit
in CHCR.
• Transfer ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR
forcibly aborts transfer on all channels. The TE bit is not set. All channels abort their transfer
according to the conditions in (a) to (d) in section 12.3.7, DMA Transfer Ending Conditions, as
in NMI interrupt generation. In this case, the values in SAR, DAR, and DMATCR are also
updated.
Rev. 5.0, 09/03, page 419 of 806