SH7729R Datasheet, PDF (262/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3. When the condition is specified to occur after execution, the instruction set with the break
condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delay branch instruction, the break is generated at the
instruction that then first accepts the break.
4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
There is thus no need to set break data for an instruction fetch cycle break.
8.3.3 Break by Data Access Cycle
1. The memory cycle in which a CPU data access break occurs depend on the instruction.
2. The relationship between the data access cycle address and the comparison condition for
operand size is shown in table 8.2:
Table 8.2 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Longword
Word
Byte
Address Compared
Compares break address register bits 31–2 to address bus bits 31–2
Compares break address register bits 31–1 to address bus bits 31–1
Compares break address register bits 31–0 to address bus bits 31–0
This means that when address H'00001003 is set without specifying the size condition, for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. When the data value is included in the break condition on channel B:
When the data value is included in the break condition, longword, word, or byte is specified as
the operand size in the break bus cycle registers (BBRA and BBRB). When data values are
included in break conditions, a break is generated when the address conditions and data
conditions both match. To specify byte data for this case, set the same data in two bytes at bits
15–8 and bits 7–0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored.
4. When the DMAC data access is included in the break condition:
When the address is included in the break condition on DMAC data access, the operand size of
the break bus cycle registers (BBRA and BBRB) should be byte, word, or no specified operand
size. When the data value is included, select either byte or word.
Rev. 5.0, 09/03, page 216 of 806