SH7729R Datasheet, PDF (531/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Bit 5: ORER Description
0
Receiving is in progress or has ended normally^*1
(Initial value)
ORER is cleared to 0 when the chip is reset or enters standby mode, or when
software reads ORER after it has been set to 1, then writes 0 to ORER.
1
A receive overrun error occurred^*2
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
retains its previous value.
2. SCRDR continues to hold the data received before the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in
asynchronous mode.
Bit 4: FER
0
1
Description
Receiving is in progress or has ended normally
(Initial value)
Clearing the RE bit to 0 in the serial control register does not affect the FER bit,
which retains its previous value.
FER is cleared to 0 when the chip is reset or enters standby mode, or when
software reads FER after it has been set to 1, then writes 0 to FER.
A receive framing error occurred
When the stop bit length is two bits, only the first bit is checked. The second stop
bit is not checked. When a framing error occurs, the SCI transfers the receive
data into SCRDR but does not set RDRF. Serial receiving cannot continue while
FER is set to 1. In synchronous mode, serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0.
Rev. 5.0, 09/03, page 485 of 806