SH7729R Datasheet, PDF (105/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.5 Instruction Set
2.5.1 CPU Instruction Set
The SH-1/SH-2/SH-3 compatible instruction set consists of 68 basic instruction types divided into
six functional groups, as shown in table 2.19. Tables 2.20 to 2.25 show the instruction notation,
machine code, execution time, and function.
Table 2.19 CPU Instruction Types
Type
Data transfer
instructions
Arithmetic
operation
instructions
Kinds of
Instruction
5
21
Op Code
MOV
MOVA
MOVT
SWAP
XTRCT
ADD
ADDC
ADDV
CMP/cond
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
Function
Number of
Instructions
Data transfer
39
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Effective address transfer
T bit transfer
Upper/lower swap
Extraction of middle of linked registers
Binary addition
33
Binary addition with carry
Binary addition with overflow check
Comparison
Division
Signed division initialization
Unsigned division initialization
Signed double-precision multiplication
Unsigned double-precision multiplication
Decrement and test
Sign extension
Zero extension
Multiply-and-accumulate, double-
precision multiply-and-accumulate
Double-precision multiplication
(32 × 32 bits)
Rev. 5.0, 09/03, page 59 of 806