SH7729R Datasheet, PDF (106/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Type
Arithmetic
operation
instructions
Logic
operation
instructions
Shift
instructions
Kinds of
Instruction
21
6
12
Op Code
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
AND
NOT
OR
TAS
TST
XOR
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
SHAD
SHLD
Function
Signed multiplication (16 × 16 bits)
Unsigned multiplication (16 × 16 bits)
Sign inversion
Sign inversion with borrow
Binary subtraction
Binary subtraction with carry
Binary subtraction with underflow
Logical AND
Bit inversion
Logical OR
Memory test and bit setting
Logical AND and T bit setting
Exclusive logical OR
1-bit left shift
1-bit right shift
1-bit left shift with T bit
1-bit right shift with T bit
Arithmetic 1-bit left shift
Arithmetic 1-bit right shift
Logical 1-bit left shift
Logical n-bit left shift
Logical 1-bit right shift
Logical n-bit right shift
Arithmetic dynamic shift
Logical dynamic shift
Number of
Instructions
33
14
16
Rev. 5.0, 09/03, page 60 of 806