SH7729R Datasheet, PDF (231/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request
has been generated.
Bit 3: DEI3R
0
1
Description
DEI3 interrupt request not generated
DEI3 interrupt request generated
(Initial value)
Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request
has been generated.
Bit 2: DEI2R
0
1
Description
DEI2 interrupt request not generated
DEI2 interrupt request generated
(Initial value)
Bit 1—DEI1 Interrupt Request (DEI1R): Indicates whether a DEI1 (DMAC) interrupt request
has been generated.
Bit 1: DEI1R
0
1
Description
DEI1 interrupt request not generated
DEI1 interrupt request generated
(Initial value)
Bit 0—DEI0 Interrupt Request (DEI0R): Indicates whether a DEI0 (DMAC) interrupt request
has been generated.
Bit 0: DEI0R
0
1
Description
DEI0 interrupt request not generated
DEI0 interrupt request generated
(Initial value)
7.3.8 Interrupt Request Register 2 (IRR2)
IRR2 is an 8-bit read-only register that indicates whether an A/D converter or SCIF interrupt
request has been generated. This register is initialized to H'00 by a power-on reset or manual reset,
but is not initialized in standby mode.
Bit: 7
6
5
4
3
2
1
0
—
—
—
ADIR TXI2R BRI2R RXI2R ERI2R
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Rev. 5.0, 09/03, page 185 of 806