SH7729R Datasheet, PDF (613/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 7—Receive Error (ER): Indicates the occurrence of a framing error, or of a parity error when
receiving data that includes parity.
Bit 7: ER
Description
0
Receiving is in progress or has ended normally^*1
(Initial value)
ER is cleared to 0 when the chip is reset or enters standby mode, or when 0 is
written after 1 is read from ER
1
A framing error or parity error has occurred
ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit
of the received data is 1 at the end of one data receive operation^*2, or when the
total number of 1s in the receive data plus parity bit does not match the even/odd
parity specified by the O/E bit in SCSMR
Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous
value. Even if a receive error occurs, the receive data is transferred to SCFRDR and
the receive operation is continued. Whether or not the data read from SCRDR includes
a receive error can be detected by the FER and PER bits in SCSSR.
2. In stop mode, only the first stop bit is checked; the second stop bit is not checked.
Bit 6—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, SCFTDR did not contain valid data, so transmission has ended.
Bit 6: TEND
0
1
Description
Transmission is in progress
TEND is cleared to 0 when data is written in SCFTDR
End of transmission
(Initial value)
TEND is set to 1 when the chip is reset or enters standby mode, when TE is
cleared to 0 in the serial control register (SCSCR), or when SCFTDR does not
contain receive data when the last bit of a one-byte serial character is transmitted
Rev. 5.0, 09/03, page 567 of 806