SH7729R Datasheet, PDF (331/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 0: A6PCM
0
1
Description
Physical space area 6 accessed as ordinary memory
Physical space area 6 accessed as PCMCIA space
(Initial value)
11.2.2 Bus Control Register 2 (BCR2)
Bus control register 2 (BCR2) is a 16-bit readable/writable register that selects the bus size of each
area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Do not access external memory outside area 0 until BCR2 register initialization is
complete.
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
— A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0
0
1
1
1
1
1
1
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
A3SZ1 A3SZ0 A2SZ1 A2SZ0 —
—
—
—
Initial value: 1
1
1
1
0
0
0
0
R/W: R/W R/W R/W R/W
R
R
R
R
Bits 15, 14, 3, 2, 1, and 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Bits 2n + 1, 2n—Area n (2–6) Bus Size Specification (AnSZ1, AnSZ0): Specify the bus size of
physical space area n (n = 2 to 6).
Bit 2n + 1: AnSZ1
0
1
0
1
Bit 2n: AnSZ0
0
1
0
1
0
1
0
1
Port A/B
Not used
Used
Description
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Longword (32-bit) size
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Reserved (Setting prohibited)
Rev. 5.0, 09/03, page 285 of 806