SH7729R Datasheet, PDF (15/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
17.4 SCIF Interrupts
Table 17.10 SCIF
Interrupt Sources
Page
594
Description
Description amended
When the TDFE flag in the serial status register (SCSSR) is set to
1, a TXI interrupt request is generated. The DMAC can be
activated and data transfer performed when this interrupt is
generated. When data exceeding the transmit trigger number is
written to the transmit data register (SCFTDR) by the DMAC, 1 is
read from the TDFE flag, after which 0 is written to it to clear it.
17.5 Usage Notes
595
20.13.2 SC Port Data 654
Register (SCPDR)
When the RDF flag in SCSSR is set to 1, an RXI interrupt request
is generated. The DMAC can be activated and data transfer
performed when the RDF flag in SCSSR is set to 1. When
receive data less than the receive trigger number is read from the
receive data register (SCFRDR) by the DMAC, 1 is read from the
RDF flag, after which 0 is written to it to clear it.
Table amended
(Before)Priority on Reset Release →(After)Priority
Description amended
1. SCFTDR Writing and TDFE Flag:
However, if the number of data bytes written to SCFTDR is equal
to or less than the transmit trigger number, the TDFE flag will be
set to 1 again even after having been cleared to 0. TDFE clearing
should therefore be carried out after data exceeding the specified
transmit trigger number has been written to SCFTDR.
Title amended
Rev. 5.0, 09/03, page xv of xlvi