SH7729R Datasheet, PDF (24/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

10.5.3 Notes on Changing the Frequency........................................................................ 259
10.6 Overview of WDT............................................................................................................. 260
10.6.1 Block Diagram of WDT ....................................................................................... 260
10.6.2 Register Configuration ......................................................................................... 260
10.7 WDT Registers .................................................................................................................. 261
10.7.1 Watchdog Timer Counter (WTCNT) ................................................................... 261
10.7.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 261
10.7.3 Notes on Register Access ..................................................................................... 263
10.8 Using the WDT ................................................................................................................. 264
10.8.1 Canceling Standby................................................................................................ 264
10.8.2 Changing the Frequency....................................................................................... 265
10.8.3 Using Watchdog Timer Mode .............................................................................. 265
10.8.4 Using Interval Timer Mode .................................................................................. 265
10.9 Notes on Board Design...................................................................................................... 266
Section 11 Bus State Controller (BSC) ......................................................................... 269
11.1 Overview ........................................................................................................................... 269
11.1.1 Features ................................................................................................................ 269
11.1.2 Block Diagram ..................................................................................................... 271
11.1.3 Pin Configuration ................................................................................................. 272
11.1.4 Register Configuration ......................................................................................... 274
11.1.5 Area Overview ..................................................................................................... 275
11.1.6 PCMCIA Support................................................................................................. 278
11.2 BSC Registers.................................................................................................................... 281
11.2.1 Bus Control Register 1 (BCR1)............................................................................ 281
11.2.2 Bus Control Register 2 (BCR2)............................................................................ 285
11.2.3 Wait State Control Register 1 (WCR1) ................................................................ 286
11.2.4 Wait State Control Register 2 (WCR2) ................................................................ 287
11.2.5 Individual Memory Control Register (MCR) ....................................................... 291
11.2.6 PCMCIA Control Register (PCR) ........................................................................ 294
11.2.7 Synchronous DRAM Mode Register (SDMR)..................................................... 298
11.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 299
11.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 301
11.2.10 Refresh Time Constant Register (RTCOR) .......................................................... 302
11.2.11 Refresh Count Register (RFCR)........................................................................... 302
11.2.12 Cautions on Accessing Refresh Control Related Registers .................................. 303
11.2.13 MCS0 Control Register (MCSCR0)..................................................................... 304
11.2.14 MCS1 Control Register (MCSCR1)..................................................................... 305
11.2.15 MCS2 Control Register (MCSCR2)..................................................................... 305
11.2.16 MCS3 Control Register (MCSCR3)..................................................................... 305
11.2.17 MCS4 Control Register (MCSCR4)..................................................................... 305
11.2.18 MCS5 Control Register (MCSCR5)..................................................................... 305
11.2.19 MCS6 Control Register (MCSCR6)..................................................................... 305
Rev. 5.0, 09/03, page xxiv of xlvi