SH7729R Datasheet, PDF (299/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

10.3 Clock Operating Modes
Table 10.3 shows the relationship between the mode control pin (MD2–MD0) combinations and
the clock operating modes. Table 10.4 shows the usable frequency ranges in the clock operating
modes.
Table 10.3 Clock Operating Modes
Pin Values
Mode MD2 MD1 MD0
0
00
0
1
001
2
010
7
111
— Values except
above
Clock I/O
PLL2 PLL1 Divider 1 Divider 2 CKIO
Source Output On/Off On/Off Input Input Frequency
EXTAL CKIO
On,
On
multi-
plication
ratio: 1
PLL1
output
PLL1
(EXTAL)
EXTAL CKIO
On,
On
multi-
plication
ratio: 4
PLL1
output
PLL1
(EXTAL) × 4
Crystal CKIO
oscillator
On,
On
multi-
plication
ratio: 4
PLL1
output
PLL1
(Crystal) × 4
CKIO —
Off
On PLL1 PLL1 (CKIO)
output
Reserved (Setting prohibited)
Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by
PLL circuit 2 before being supplied inside the chip. PLL circuit 1 is constantly on, and there are
no frequency range restrictions compared to mode 3. An input clock frequency of 25 MHz to
66.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by
PLL circuit 2 before being supplied inside the chip, allowing a low-frequency external clock to be
used. An input clock frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency
range is 25 MHz to 66.67 MHz.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Rev. 5.0, 09/03, page 253 of 806