SH7729R Datasheet, PDF (805/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Appendix A Pin Functions
A.1 Pin States
Table A.1 shows pin states during resets, power-down states, and the bus-released state.
Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State
Category
Pin
Clock
System control
Interrupt
EXTAL
XTAL
CKIO
EXTAL2
XTAL2
CAP1, CAP2
RESETP
RESETM
BREQ
BACK
MD[5:0]
CA
STATUS[1:0]/PTJ[7:6]
IRQ[3:0]/IRL[3:0]/
PTH[3:0]
IRQ4/ PTH[4]
NMI
IRLS[3:0]/PTF[3:0]/
PINT[11:8]
MCS[7:0]/PTC[7:0]/
PINT[7:0]
TCK/PTF4/PINT12
TDI/PTFS/PINT13
TMS/PTF6/PINT14
TRST/PTF7/PINT15
IRQOUT
Reset
Power-On Manual
Reset Reset
I
O^*1
IO^*1
I
O^*1
IO^*1
I
I
O
O
—
—
I
I
I
I
I
I
O
O
I
I
I
I
O
OP^*2
V^*7
I
Power-Down
Standby Sleep
I
O^*1
IO^*1
I
O
—
I
I
I
O
I
I
OP^*2
I
I
O^*1
IO^*1
I
O
—
I
I
I
O
I
I
OP^*2
I
Bus
Released
I
O^*1
IO^*1
I
O
—
I
I
I
L
I
I
OP^*2
I
V^*7
I
I
I
I
I
I
I
I
I
V
I
IZ
I
I
V
OP^*2 ZH^*10 K^*2 OP^*2
ZP^*2
IV
I
IZ
I
I
IV
I
IZ
I
I
IV
I
IZ
I
I
IV
I
IZ
I
I
O
O
O
O
O
Rev. 5.0, 09/03, page 759 of 806