SH7729R Datasheet, PDF (44/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 16.3 Register Settings for Smart Card Interface ............................................................. 541
Table 16.4 Relationship of n to CKS1 and CKS0..................................................................... 543
Table 16.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n = 0)................................. 543
Table 16.6 Examples of SCBRR Settings for Bit Rate B (Bits/s) (n = 0)................................. 543
Table 16.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ....................... 544
Table 16.8 Register Set Values and SCK Pin ........................................................................... 544
Table 16.9 Smart Card Mode Operating State and Interrupt Sources....................................... 551
Table 17.1 SCIF Pins................................................................................................................ 559
Table 17.2 SCIF Registers ........................................................................................................ 560
Table 17.3 SCSMR Settings ..................................................................................................... 571
Table 17.4 Bit Rates and SCBRR Settings ............................................................................... 572
Table 17.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) ............................................................................................ 576
Table 17.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)................. 577
Table 17.7 SCSMR Settings and SCIF Communication Formats ............................................ 581
Table 17.8 SCSCR Settings and SCIF Clock Source Selection................................................ 582
Table 17.9 Serial Communication Formats .............................................................................. 582
Table 17.10 SCIF Interrupt Sources ........................................................................................... 594
Table 18.1 IrDA Pins................................................................................................................ 603
Table 18.2 IrDA Registers ........................................................................................................ 604
Table 19.1 List of Multiplexed Pins ......................................................................................... 609
Table 19.2 Pin Function Controller Registers........................................................................... 613
Table 20.1 Port A Register ....................................................................................................... 631
Table 20.2 Port A Data Register (PADR) Read/Write Operations ........................................... 632
Table 20.3 Port B Register........................................................................................................ 633
Table 20.4 Port B Data Register (PBDR) Read/Write Operations ........................................... 634
Table 20.5 Port C Register........................................................................................................ 635
Table 20.6 Port C Data Register (PCDR) Read/Write Operations ........................................... 636
Table 20.7 Port D Register ....................................................................................................... 637
Table 20.8 Port D Data Register (PDDR) Read/Write Operations ........................................... 638
Table 20.9 Port E Register........................................................................................................ 639
Table 20.10 Port E Data Register (PEDR) Read/Write Operations ............................................ 640
Table 20.11 Port F Register ........................................................................................................ 641
Table 20.12 Port F Data Register (PFDR) Read/Write Operations ............................................ 642
Table 20.13 Port G Register ....................................................................................................... 643
Table 20.14 Port G Data Register (PGDR) Read/Write Operations ........................................... 644
Table 20.15 Port H Register ....................................................................................................... 645
Table 20.16 Port H Data Register (PHDR) Read/Write Operations ........................................... 646
Table 20.17 Port J Register......................................................................................................... 647
Table 20.18 Port J Data Register (PJDR) Read/Write Operations.............................................. 648
Table 20.19 Port K Register ....................................................................................................... 649
Table 20.20 Port K Data Register (PKDR) Read/Write Operations ........................................... 650
Table 20.21 Port L Register........................................................................................................ 651
Rev. 5.0, 09/03, page xliv of xlvi