SH7729R Datasheet, PDF (614/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from the
transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data
in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and
TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is
enabled.
Bit 5: TDFE
Description
0
The quantity of transmit data written to SCFTDR is greater than the specified
transmission trigger number
(Initial value)
TDFE is cleared to 0 when data exceeding the specified transmission trigger
number is written to SCFTDR, or when software reads TDFE after it has been
set to 1, then writes 0 to TDFE
1
The quantity of transmit data in SCFTDR is less than the specified transmission
trigger number*
TDFE is set to 1 by a reset or in standby mode, or when the quantity of transmit
data in SCFTDR becomes less than the specified transmission trigger number as
a result of transmission
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be
written when TDFE is 1 is “16 minus the specified transmission trigger number”. If an
attempt is made to write additional data, the data is ignored. The quantity of data in
SCFTDR is indicated by the upper 8 bits of SCFTDR.
Bit 4—Break Detection (BRK): Indicates that a break signal has been detected in receive data.
Bit 4: BRK
Description
0
No break signal received
(Initial value)
BRK is cleared to 0 when the chip is reset or enters standby mode, or when
software reads BRK after it has been set to 1, then writes 0 to BRK
1
Break signal received*
BRK is set to 1 when data including a framing error is received, and a framing
error occurs with space 0 in the subsequent receive data
Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after
detection. When the break ends and the receive signal becomes mark 1, the transfer of
receive data resumes. The receive data of a frame in which a break signal is detected is
transferred to SCFRDR. After this, however, no receive data is transferred until a break
ends with the received signal being mark 1, and the next data is received.
Rev. 5.0, 09/03, page 568 of 806