SH7729R Datasheet, PDF (120/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 2.26 Added CPU System Control Instructions
Instruction
SETRC #imm
SETRC Rn
LDRS @(disp,PC)
LDRE @(disp,PC)
STC MOD,Rn
STC RS,Rn
STC RE,Rn
STS DSR,Rn
STS A0,Rn
STS X0,Rn
STS X1,Rn
STS Y0,Rn
STS Y1,Rn
STS.L DSR,@-Rn
STS.L A0,@-Rn
STS.L X0,@-Rn
STS.L X1,@-Rn
STS.L Y0,@-Rn
STS.L Y1,@-Rn
STC.L MOD,@-Rn
STC.L RS,@-Rn
STC.L RE,@-Rn
LDS.L @Rn+,DSR
LDS.L @Rn+,A0
LDS.L @Rn+,X0
LDS.L @Rn+,X1
LDS.L @Rn+,Y0
LDS.L @Rn+,Y1
LDC.L @Rn+,MOD
LDC.L @Rn+,RS
Instruction Code
Operation
10000010iiiiiiii imm → RC (of SR)
0100nnnn00010100 Rn[11:0] → R C (of SR)
10001100dddddddd (disp × 2 + PC) → RS
10001110dddddddd (disp × 2 + PC) → RE
0000nnnn01010010 MOD → Rn
0000nnnn01100010 RS → Rn
0000nnnn01110010 RE → Rn
0000nnnn01101010 DSR → Rn
0000nnnn01111010 A0 → Rn
0000nnnn10001010 X0 → Rn
0000nnnn10011010 X1 → Rn
0000nnnn10101010 Y0 → Rn
0000nnnn10111010 Y1 → Rn
0100nnnn01100010 Rn – 4 → Rn, DSR → (Rn)
0100nnnn01110010 Rn – 4 → Rn, A0 → (Rn)
0100nnnn10000010 Rn – 4 → Rn, X0 → (Rn)
0100nnnn10010010 Rn – 4 → Rn, X1 → (Rn)
0100nnnn10100010 Rn – 4 → Rn, Y0 → (Rn)
0100nnnn10110010 Rn – 4 → Rn, Y1 → (Rn)
0100nnnn01010011 Rn – 4 → Rn, MOD → (Rn)
0100nnnn01100011 Rn – 4 → Rn, RS → (Rn)
0100nnnn01110011 Rn – 4 → Rn, RE → (Rn)
0100nnnn01100110 (Rn) → DSR, Rn + 4 → Rn
0100nnnn01110110 (Rn) → A0, Rn + 4 → Rn
0100nnnn10000110 (Rn) → X0, Rn + 4 → Rn
0100nnnn10010110 (Rn) → X1, Rn + 4 → Rn
0100nnnn10100110 (Rn) → Y0, Rn + 4 → Rn
0100nnnn10110110 (Rn) → Y1, Rn + 4 → Rn
0100nnnn01010111 (Rn) → MOD, Rn + 4 → Rn
0100nnnn01100111 (Rn) → RS, Rn + 4 → Rn
Execu-
tion
States
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
5
5
T Bit
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Rev. 5.0, 09/03, page 74 of 806