SH7729R Datasheet, PDF (265/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 8.3 BSA Values Stored in Exception Handling before Execution of Branch
Destination Instruction
Branch
Delay
No delay
Branch Destination
(Dest)
4n
4n + 2
4n or 4n + 2
BSA
4n
4n + 2
4n
Branch Source Address Calculable
by Means of BRSR and BRFR
Exec = IA = BSA – 2 × PID
Dest = BSA
Exec = IA = BSA – 2 × PID
If PID is an odd number, the value incremented by 2 indicates the instruction buffer, but the
equations in the table do not take this into account. Therefore, the calculation can be performed
using the values of BSA stored in BRSR and PID stored in BRFR.
3. The location indicated by IA, the address prior to the branch, depends on the type of branch.
a. Branch instruction: Branch instruction address
b. Repeat loop: Second-before-last instruction of the repeat loop
Repeat_Start: inst (1) ;----->BRDR
inst (2) ;
:
inst (n–1) ;----->Address calculated from BRSR and BRFR
Repeat End: inst (n) ;
c. Interrupt: Instruction executed immediately before the interrupt
The start address of the interrupt routine is stored in BRDR.
In a repeat loop consisting of no more than three instructions, an instruction fetch cycle is not
generated. A PC trace is invalid, since the branch destination address is unknown.
4. BRSR, BRDR, and BRFR have a four-queue structure. When reading addresses stored in a PC
trace, reads are performed from the head of the queue. BRFR, BRSR, and BRDR are read in
that order. After BRDR is read, the queue shifts by one. BRSR and BRDR should be read by
longword access. Also, the PC trace has a trace pointer, which initially points to the bottom of
the queues. The first pair of branch addresses will be stored at the bottom of the queues, then
push up when next pairs come into the queues. The trace pointer will points to the next branch
address to be executed, unless it got push out of the queues. When the branch address has been
executed, the trace pointer will shift down to next pair of addresses, until it reaches the bottom
of the queues. After switching the PCTE bit (in BRCR) off and on, the values in the queues are
invalid. The read pointer stay at the position before PCTE is switched, but the trace pointer
restart at the bottom of the queues.
Rev. 5.0, 09/03, page 219 of 806