SH7729R Datasheet, PDF (695/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.11 Port K
Port K is an 8-bit input/output port with the pin configuration shown in figure 20.10. Each pin has
an input pull-up MOS, which is controlled by the port K control register (PKCR) in the PFC.
Port K
PTK7 (input/output) / WE3 (output) / DQMUU (output) / ICIOWR (output)
PTK6 (input/output) / WE2 (output) / DQMUL (output) / ICIORD (output)
PTK5 (input/output) / CKE (output)
PTK4 (input/output) / BS (output)
PTK3 (input/output) / CS5 (output) / CE1A (output)
PTK2 (input/output) / CS4 (output)
PTK1 (input/output) / CS3 (output)
PTK0 (input/output) / CS2 (output)
Figure 20.10 Port K
20.11.1 Register Description
Table 20.19 summarizes the port K register.
Table 20.19 Port K Register
Name
Abbreviation R/W Initial Value Address
Access Size
Port K data register
PKDR
R/W H'00
H'04000132 8
(H'A4000132)^*
Notes: This register is located in area 1 of physical space. Therefore, when the cache is on, either
access this register from the P2 area of logical space or else make an appropriate setting
using the MMU so that this register is not cached.
* When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.0, 09/03, page 649 of 806