SH7729R Datasheet, PDF (741/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

23.4 UDI Operation
23.4.1 TAP Controller
Figure 23.2 shows the internal states of the TAP controller. State transitions basically conform
with the JTAG standard.
1 Test-logic-reset
0
1
0 Run-test/idle
1
Select-DR-scan
1
Capture-DR
0
Shift-DR 0
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
10
1
Select-IR-scan
0
1
Capture-IR
0
Shift-IR 0
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
10
Figure 23.2 TAP Controller State Transitions
Note:
The transition condition is the TMS value at the rising edge of TCK. The TDI value is
sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. The TDO
value changes at the TCK falling edge. The TDO is at high impedance, except with shift-
DR (shift-SR) and shift-IR states. During the change to TRST = 0, there is a transition to
test-logic-reset asynchronously with TCK.
Rev. 5.0, 09/03, page 695 of 806