SH7729R Datasheet, PDF (551/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 15.9 shows an example of SCI transmit operation in asynchronous mode.
1
Serial
data
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data bit bit 1
D₁
D₇
0/1
1
Idle (mark)
state
TDRE
TEND
TXI interrupt
request
generated
TXI interrupt
handler writes
data to SCTDR
and clears
TDRE bit to 0
TXI interrupt
request
generated
TEI interrupt
request
generated
1 frame
Figure 15.9 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figure 15.10 shows a sample flowchart for
receiving serial data. The procedure for receiving serial data after enabling the SCI for reception
is:
1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER and
FER bits in SCSSR to identify the error. After executing the necessary error handling, clear
ORER, PER and FER to 0. Receiving cannot resume if ORER, PER or FER remains set to 1.
When a framing error occurs, the RxD pin can be read to detect the break state.
2. SCI status check and receive-data read: Read the serial status register (SCSSR), check that
RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear
RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from
0 to 1.
3. To continue receiving serial data: Read the RDRF and SCRDR bits and clear RDRF to 0
before the stop bit of the current frame is received.
Rev. 5.0, 09/03, page 505 of 806