SH7729R Datasheet, PDF (258/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 31—BRSR Valid Flag (SVF): Indicates whether the address and the pointer that indicates the
branch source address can be calculated. When a branch source address is fetched, this flag is set
to 1. This flag is cleared to 0 by reading BRSR.
Bit 31: SVF
0
1
Description
BRSR register value is invalid
BRSR register value is valid
(Initial value)
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7).
These bits indicate the instruction buffer number which stores the last instruction executed before
a branch.
Bits 30 to 28:
PID
Even
Odd
Description
PID indicates the instruction buffer number
PiD+2 indicates the instruction buffer number
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last address
fetched before a branch.
Rev. 5.0, 09/03, page 212 of 806