SH7729R Datasheet, PDF (10/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
5.4.2 Data Array
Page
152
Description
Description amended
The address array is mapped to H'F1000000 to H'F1FFFFFF. To
access an element of the data array, the 32-bit address field (for
read/write access) and 32-bit data field (for write access) must be
specified. The address field specifies the information that selects
the entry to be accessed; the data field specifies the longword
data to be written to the data array.
In the address field, specify the entry's address in bits 11-4, L in
bits 3-2 to indicate the longword's position within a line (which
consists of 16 bytes), W in bits 13-12 to select the way, and H'F1
in bits 31-24 to indicate access to the data array. The L bits (3-2)
specification is in the following form: 00 is longword 0, 01 is
longword 1, 10 is longword 2, and 11 is longword 3. Settings for
the W bits (13-12) are as follows: 00 is way 0, 01 is way 1, 10 is
way 2, and 11 is way 3. Since access is not allowed crossing
longword boundaries, always set 00 in bits 1-0 of the address
field.
The following two operations on the data array are possible. Note
that these operations will not change the information in the
address array.
(1) Data Array Read
Reads the data at the position selected by the L bits (3-2) of the
address field from the entry that corresponds to the entry address
and way that were specified in the address field.
(2) Data Array Write
Writes the longword data set in the data field into the entry that
corresponds to the entry address and way that were specified in
the address field. The longword data will be written to the entry at
the position selected by the L bits (3-2) of the address field.
Rev. 5.0, 09/03, page x of xlvi