SH7729R Datasheet, PDF (196/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

5.3.2 Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
transfer unit is 32 bits. LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one
least recently used. Entries are updated in 16-byte units. When the desired instruction or data that
caused the miss is loaded from external memory to the cache, the instruction or data is transferred
to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is
cleared to 0 and the V bit is set to 1.
5.3.3 Write Access
Write Hit: In a write access in write-back mode, the data is written to the cache and the U bit of
the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is
issued. In write-through mode, the data is written to the cache and an external memory write cycle
is issued.
Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the
entry is updated. The way to be replaced is the one least recently used. When the U bit of the entry
to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer.
The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1. After the
cache completes its fill cycle, the write-back buffer writes the entry back to the memory. In write-
through mode, no write to cache occurs in a write miss; the write is only to the external memory.
5.3.4 Write-Back Buffer
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. During the write-back cycles, the cache can be accessed. The write-back buffer
can hold one line of cache data (16 bytes) and its physical address. Figure 5.5 shows the
configuration of the write-back buffer.
PA (31−4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31−4): Physical address written to external memory
Longword 0−3: The line of cache data to be written to
external memory
Figure 5.5 Write-Back Buffer Configuration
Rev. 5.0, 09/03, page 150 of 806