SH7729R Datasheet, PDF (409/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
T₁
T₂ Twait T₁
T₂ Twait T₁
T₂
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Area m read
Area n space read
Area n space write
Area m inter-access wait specification Area n inter-access wait specification
Figure 11.40 Waits between Access Cycles
11.3.8 Bus Arbitration
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not
released during burst transfers for cache fills or TAS instruction execution between the read cycle
and write cycle. Bus arbitration is not executed in multiple bus cycles that are generated when the
data bus width is shorter than the access size; i.e. in the bus cycles when longword access is
executed for the 8-bit memory. At the negation of BREQ, BACK is negated and bus use is
restarted. See Appendix A.1, Pin States, for the pin states when the bus is released.
The SH7729R sometimes needs to retrieve a bus it has released. For example, when memory
generates a refresh request or an interrupt request internally, the SH7729R must perform the
appropriate processing. The SH7729R has a bus request signal (IRQOUT) for this purpose. When
it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus release
request receive the assertion of the IRQOUT signal and negate the BREQ signal to release the bus.
The SH7729R retrieves the bus and carries out the processing.
Rev. 5.0, 09/03, page 363 of 806