SH7729R Datasheet, PDF (678/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.2.2 Port A Data Register (PADR)
Bit:
Initial value:
R/W:
7
PA7DT
0
R/W
6
PA6DT
0
R/W
5
PA5DT
0
R/W
4
PA4DT
0
R/W
3
PA3DT
0
R/W
2
PA2DT
0
R/W
1
PA1DT
0
R/W
0
PA0DT
0
R/W
The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins
PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function
is general output port, if the port is read the value of the corresponding PADR bit is returned
directly. When the function is general input port, if the port is read the corresponding pin level is
read. Table 20.2 shows the function of PADR.
PADR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Table 20.2 Port A Data Register (PADR) Read/Write Operations
PAnMD1 PAnMD0 Pin State
Read
Write
0
0
Other function PADR value Value is written to PADR, but does not
(See table 19.1)
affect pin state
1
Output
PADR value Write value is output from pin.
1
0
Input (Pull-up Pin state
Value is written to PADR, but does not
MOS on)
affect pin state
1
Input (Pull-up Pin state
Value is written to PADR, but does not
MOS off)
affect pin state
(n = 7 to 0)
Rev. 5.0, 09/03, page 632 of 806