SH7729R Datasheet, PDF (255/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle
condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 to this bit.
Bit 13:
SCMFDA
0
1
Description
DMAC cycle condition for channel A is not matched
DMAC cycle condition for channel A is matched
(Initial value)
Bit 12—DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle
condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 to this bit.
Bit 12:
SCMFDB
0
1
Description
DMAC cycle condition for channel B is not matched
DMAC cycle condition for channel B is matched
(Initial value)
Bit 11—PC Trace Enable (PCTE): Enables a PC trace.
Bit 11: PCTE
0
1
Description
PC trace disabled
PC trace enabled
(Initial value)
Bit 10—PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
Bit 10: PCBA
0
1
Description
PC break of channel A is set before instruction execution
PC break of channel A is set after instruction execution
(Initial value)
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Data Break Enable B (DBEB): Selects whether or not the data bus condition is included
in the channel B break condition.
Bit 7: DBEB
0
1
Description
Data bus condition not included in channel B condition
Data bus condition included in channel B condition
(Initial value)
Rev. 5.0, 09/03, page 209 of 806